Date/Time
Date(s) - 09/10/2014
2:00 pm - 4:45 pm
Location
Room G.07A, Informatics Forum, 10 Crichton Street, Edinburgh
A series of Seminars will take place on Thursday 9th October as follows:
2.00-2.45 : Aaron Smith (Microsoft Research Seattle) – Accelerating Datacenter Services with Reconfigurable Logic
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3.00-3.45 : Dimitrios Vytiniotis (Microsoft Research Cambridge) – Ziria: wireless programming for hardware dummies
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4.00-4.45 : Bjoern Franke (University of Edinburgh) – Targeting extensible processors for visible light communication and other signal processing applications
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2.00-2.45
Title: Accelerating Datacenter Services with Reconfigurable Logic
Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurable fabric at Microsoft to accelerate portions of large-scale software services. In this talk I will describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and discuss its efficacy in accelerating the Bing web search engine along with future plans to improve the programmability of the fabric.
Bio:
Aaron Smith is a member of the Computer Architecture Group at Microsoft Research. He is broadly interested in optimizing compilers, computer architecture and reconfigurable computing. Over the past 15 years he has led multiple industrial and research compiler projects at Metrowerks/Freescale Semiconductor, The University of Texas at Austin and Microsoft. He received his PhD in Computer Science from UT-Austin in 2009 and is currently serving as co-General Chair of CGO 2015.
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3.00-3.45
Title: Ziria: wireless programming for hardware dummies
Software-defined radio (SDR) brings the flexibility of software to the domain of wireless protocol design, promising both an ideal platform for research and innovation and the rapid deployment of new protocols on existing hardware. Most existing SDR platforms require careful hand-tuning of low-level code to be useful in the real world. In this talk I will describe Ziria, an SDR platform that is both easily programmable and performant. Ziria introduces a programming model that builds on ideas from functional programming and that is tailored to wireless physical layer tasks. The model captures the inherent and important distinction between data and control paths in this domain. I will describe the programming model, give an overview of the execution model, compiler optimizations, and current work on parallelization and scheduling reconfigurable pipelines. We have used Ziria to produce an implementation of 802.11a/g and a partial implementation of LTE.
Bio:
Dimitrios Vytiniotis is a researcher in the Programming Principles and Tools group in Microsoft Research Cambridge. His research work is in the areas of type systems and type inference, functional programming, language design and implementation, domain-specific languages, dependent types and formal verification, and using programming languages techniques and principles to better program or optimize systems. Dimitrios holds a PhD from the University of Pennsylvania and an ECE degree from NTUA, Athens.
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4.00-4.45
Title: Targeting extensible processors for visible light communication and other signal processing applications
The automatic generation of instruction set extensions (ISEs) to provide application-specific acceleration for embedded processors has been a productive area of research in recent years. The use of automatic algorithms, however, results in instructions that are radically different from those found in conventional ISAs. This has resulted in a gap between the hardware’s capabilities and the compiler’s ability to exploit them. In this talk we present an innovative high-level compiler pass that uses subgraph isomorphism checking to exploit these complex instructions. An extended code generator enables the reuse of ISEs designed for one application in another, which may be a newer version of the same application or a different one from the same domain. Operating in a separate pass permits computationally expensive techniques to be applied that are uniquely suited for mapping complex instructions, but unsuitable for conventional instruction selection. We demonstrate that this targeted use of an expensive algorithm effectively controls overall compilation time. The existing, mature, compiler back-end can then handle the remainder of the compilation. We motivate this work by the recent work within the compiler and architecture group within ICSA@Edinburgh on a system-on-chip for visible light communication, which comprises extensible, embedded processing cores alongside more coarse-grained accelerators.
